Synopsys VCS
HDL simulator for SystemVerilog, Verilog and VHDL chip verification
Launched 1 week agosynopsys.com
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About Synopsys VCS
Synopsys VCS is a simulator that chip design teams use to check ASIC and SoC designs written in SystemVerilog, Verilog and VHDL before manufacturing. Verification engineers run test benches against a design to catch bugs early, when fixes are cheap. The tool sits inside the wider Synopsys silicon design toolchain and targets large, complex chips where simulation speed affects schedules. It is aimed at semiconductor companies and hardware verification groups.
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